High Efficiency Linear Power Amplifiers: Analysis, Linearization and Implementation a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

............................................................................................................................. iv Acknowledgments............................................................................................................... v List of Tables....................................................................................................................viii List of Figures .................................................................................................................... ix Chapter 1: Introduction ....................................................................................................... 1 1.1 Basics of power amplifiers and classes ..................................................................... 3 1.2 Basics of nonlinearity................................................................................................ 9 1.3 Basics of linearization ............................................................................................. 12 1.4 Basics of signal and modulation dynamic range and effects on efficiency ............ 17 Chapter 2: More on PA nonlinearity and its effects on modulated signals....................... 19 2.1 Quasistatic versus dynamic nonlinearity................................................................. 21 2.2 A very fast method for simulating quasistatic nonlinearity effects......................... 26 2.3 Effects of the shape of the gain compression on ACPR ......................................... 38 2.4 A search for optimum gain compression shapes..................................................... 47 Chapter 3: PA linearization from an efficiency and complexity point of view ................ 49 3.1 More on EER and newer ER techniques................................................................. 50 3.1.1 Pulse deletion modulation ................................................................................ 53 3.1.1.1 In band vs. out of band linearity trade off ................................................. 56 3.1.1.2 Signal and modulation dynamic range effects .......................................... 60 3.1.1.3 Jitter in the signal constellations ............................................................... 65 3.1.1.4 Implementation methods for classes C and D amplifiers.......................... 73 3.1.1.4.1 Feedback methods .............................................................................. 79 3.1.1.4.2 Other methods .................................................................................... 82 3.1.1.4.3 Synchronous vs. asynchronous PDM................................................. 85 3.1.2 Pulse width modulation.................................................................................... 88 3.1.3 Pulse width and amplitude modulation (PW&AM)......................................... 92 3.1.3.1 EER with envelope feedback through bias control ................................. 100 3.1.3.2 Bias controlled envelope feedback without envelope elimination.......... 102 3.1.3.3 Envelope detector dynamic range and integrator offset effects .............. 108 3.1.3.4 Bandwidth effects and dynamic nonlinearity.......................................... 116 3.1.3.5 Potential for bias-controlled ER with envelope pre-distortion................ 123 3.2 Linearization by design of shape of gain compression curve ............................... 124 3.2.1 A note on self-biasing .................................................................................... 125 3.2.2 Cascade of self-biased nonlinear stages ......................................................... 128 Chapter 4: PA module constructions and matching methods ......................................... 139 4.1 Traditional output matching network topologies and implementations................ 141 4.2 A new approach to eliminate off chip discrete passives ....................................... 144 4.2.1 HP matching networks ................................................................................... 146 4.2.2 LPHP and LPLP networks ............................................................................. 150